add me241100_svExample

.gitignore

@@ -1,9 +1,18 @@
-0_sv_learn
-1_bash_learn
 2_dpi
 3_python_learn
 4_c_re
 5_vpi
 sv_lab
 .vscode/
+
 me241200_zerotierApi/env/
+
+me241100_svExample/csrc/
+me241100_svExample/simv.daidir/
+me241100_svExample/verdiLog/
+me241100_svExample/*.log
+me241100_svExample/novas.*
+me241100_svExample/simv
+me241100_svExample/ucli.key
+me241100_svExample/vc_hdrs.h
+me241100_svExample/wave.fsdb

ReadMe.md

@@ -6,6 +6,6 @@ script work是一系列自己编选的脚本合集。
 
 | 项目                                           | 描述                                                  | 状态 | 备注 |
 | ---------------------------------------------- | ----------------------------------------------------- | ---- | ---- |
+| [me241100_svExample](./me241100_svExample)     | 使用vcs编译sv的简单例子                               | 100% |      |
 | [me241200_zerotierApi](./me241200_zerotierApi) | 使用zerotier的api获取网络信息，生成smartdns的配置文件 | 100% |      |
-|                                                |                                                       |      |      |
 

me241100_svExample/Makefile

@@ -0,0 +1,15 @@
+comp:
+	- vcs -full64 +v2k -sverilog -LDFLAGS -Wl,--no-as-needed \
+		-P ${VERDI_HOME}/share/PLI/VCS/LINUX64/novas.tab ${VERDI_HOME}/share/PLI/VCS/LINUX64/pli.a \
+		+vcs+fsdbon -debug_access+all -ntb_opts uvm-1.2 \
+		-top testbench -l compile.log -timescale=1ns/1ps\
+		testbench.sv
+
+sim:
+	- ./simv -l sim.log +fsdbfile+wave.fsdb +fsdb+no_msg+Flush +fsdb+delta +fsdb+sva_sucess +fsdb+glitch=0 +fsdb+sequential
+
+verdi:
+	- verdi -sverilog +v2k testbench.sv -ssf wave.fsdb -sswr signal.rc &
+
+clean:
+	- \rm -rf *.log *.fsdb simv.daidir

me241100_svExample/ReadMe.md

@@ -0,0 +1,29 @@
+# svExample
+
+## 概述
+
+使用vcs编译sv的简单例子。
+
+> 需要准备好vcs+verdi的仿真环境。
+
+### 特性
+
+- 生成波形
+- Makefile 管理
+
+## 快速开始
+
+### 一、仿真
+
+```bash
+make clean comp sim
+```
+
+### 二、查看波形
+
+```bash
+make verdi
+```
+
+
+

me241100_svExample/signal.rc

@@ -0,0 +1,57 @@
+Magic 271485
+Revision Verdi_O-2018.09-SP2
+
+; Window Layout <x> <y> <width> <height> <signalwidth> <valuewidth>
+viewPort 0 27 1908 399 100 65
+
+; File list:
+; openDirFile [-d delimiter] [-s time_offset] [-rf auto_bus_rule_file] path_name file_name
+openDirFile -d / "" "/home/fengbh/work/0_sv_learn/wave.fsdb"
+
+; file time scale:
+; fileTimeScale ### s|ms|us|ns|ps
+
+; signal spacing:
+signalSpacing 5
+
+; windowTimeUnit is used for zoom, cursor & marker
+; waveform viewport range
+zoom 0.000000 241424.827586
+cursor 0.000000
+marker 0.000000
+
+; user define markers
+; userMarker time_pos marker_name color linestyle
+; visible top row signal index
+top 0
+; marker line index
+markerPos 3
+
+; event list
+; addEvent event_name event_expression
+; curEvent event_name
+
+
+
+COMPLEX_EVENT_BEGIN
+
+
+COMPLEX_EVENT_END
+
+
+
+; toolbar current search type
+; curSTATUS search_type
+curSTATUS ByChange
+
+
+addGroup "G1"
+activeDirFile "" "/home/fengbh/work/0_sv_learn/wave.fsdb"
+addSignal -h 15 /testbench/clk
+addSignal -h 15 -holdScope rst_n
+addSignal -h 15 -holdScope cnt[7:0]
+addGroup "G2"
+
+; getSignalForm Scope Hierarchy Status
+; active file of getSignalForm
+

me241100_svExample/testbench.sv

@@ -0,0 +1,37 @@
+//=========================================================================== 
+// Organization : Individual Developer 
+// Filename     : testbench.sv
+// Author       : Feng Bohan
+// Create Time  : 12:54:11 2024-11-21
+// Last Modified: 13:49:31 2024-11-21
+// Abstract     :  
+//--------------------------------------------------------------------------
+// Description:
+// 
+//--------------------------------------------------------------------------
+// Modification History:
+//--------------------------------------------------------------------------
+// Rev      Date        Who         Description
+// ---      ----        ---         -----------
+// 0.0.01   2024-11-21  Feng Bohan  initial version
+//===========================================================================
+`timescale 1ns / 1ns
+module testbench;
+    reg clk=0, rst_n=1;
+    always #5 clk = ~clk;
+
+    reg [7:0] cnt;
+    always @(posedge clk or negedge rst_n)
+        if(!rst_n) 
+            cnt <= 0;
+        else 
+            cnt <= cnt +1;
+
+    initial begin
+		rst_n = 0;
+		#10 rst_n =1;
+        $display("Hello world!");
+
+        #1000 $finish;
+    end
+endmodule