//=========================================================================== 
// Organization : Individual Developer 
// Filename     : testbench.sv
// Author       : Feng Bohan
// Create Time  : 12:54:11 2024-11-21
// Last Modified: 13:49:31 2024-11-21
// Abstract     :  
//--------------------------------------------------------------------------
// Description:
// 
//--------------------------------------------------------------------------
// Modification History:
//--------------------------------------------------------------------------
// Rev      Date        Who         Description
// ---      ----        ---         -----------
// 0.0.01   2024-11-21  Feng Bohan  initial version
//===========================================================================
`timescale 1ns / 1ns
module testbench;
    reg clk=0, rst_n=1;
    always #5 clk = ~clk;

    reg [7:0] cnt;
    always @(posedge clk or negedge rst_n)
        if(!rst_n) 
            cnt <= 0;
        else 
            cnt <= cnt +1;

    initial begin
		rst_n = 0;
		#10 rst_n =1;
        $display("Hello world!");

        #1000 $finish;
    end
endmodule