comp:
	- vcs -full64 +v2k -sverilog -LDFLAGS -Wl,--no-as-needed \
		-P ${VERDI_HOME}/share/PLI/VCS/LINUX64/novas.tab ${VERDI_HOME}/share/PLI/VCS/LINUX64/pli.a \
		+vcs+fsdbon -debug_access+all -ntb_opts uvm-1.2 \
		-top testbench -l compile.log -timescale=1ns/1ps\
		testbench.sv

sim:
	- ./simv -l sim.log +fsdbfile+wave.fsdb +fsdb+no_msg+Flush +fsdb+delta +fsdb+sva_sucess +fsdb+glitch=0 +fsdb+sequential

verdi:
	- verdi -sverilog +v2k testbench.sv -ssf wave.fsdb -sswr signal.rc &

clean:
	- \rm -rf *.log *.fsdb simv.daidir