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fengbh 2025-04-14 16:50:04 +08:00
parent b2574b3f1f
commit 2a53ca9d1a
8 changed files with 238 additions and 0 deletions
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4
.gitignore vendored
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@ -6,9 +6,13 @@ simv.daidir
*.swp
.vscode
*/vc_hdrs.h
*/novas.rc
*/novas.conf
*.fsdb
2_vcs_comp/tb_lib/
2_vcs_comp/dut_lib/
2_vcs_comp/partitionlib/
2_vcs_comp/partitionlib_test2/
3_timing_check/
5_clock_block/verdiLog/

30
5_clock_block/Makefile Normal file
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LSB_RELEASE = $(shell lsb_release -is)
LSB_VERSION = $(shell lsb_release -rs)
ifeq (${LSB_RELEASE}, Ubuntu)
ifeq ($(shell echo "${LSB_VERSION}>18.04" | bc), 1)
CC = gcc-4.8
CPP = g++-4.8
else
CC = gcc
CPP = g++
endif
else
CC = gcc
CPP = g++
endif
VCC = vcs -full64 +v2k -sverilog -LDFLAGS -Wl,--no-as-needed -cc $(CC) -cpp $(CPP)\
-P ${VERDI_HOME}/share/PLI/VCS/LINUX64/novas.tab ${VERDI_HOME}/share/PLI/VCS/LINUX64/pli.a
.PHONY: clean comp all
clean:
- rm -rf csrc simv.daidir ucli.key *.log simv
comp:
$(VCC) -debug_access+all -debug_region=cell+lib -kdb -top testbench -l compile.log -timescale=1ns/1ps -f filelist.f
sim:
- ./simv -l sim.log +fsdb+all=on +fsdb+delta +fsdbfile+./wave.fsdb -ucli -i fsdb.tcl
all: comp sim

3
5_clock_block/filelist.f Normal file
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./rtl/tb.sv
./rtl/dut.sv
./rtl/chip_if.sv

2
5_clock_block/fsdb.tcl Normal file
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fsdbDumpvars 0 testbench
run

40
5_clock_block/rtl/chip_if.sv Normal file
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//===========================================================================
// Organization : Individual developer
// Filename : chip_if.sv
// Author : Feng Bohan
// Create Time : 16:14:12 2025-04-14
// Last Modified: 16:21:05 2025-04-14
// Abstract :
//--------------------------------------------------------------------------
// Description:
//
//--------------------------------------------------------------------------
// Modification History:
//--------------------------------------------------------------------------
// Rev Date Who Description
// --- ---- --- -----------
// 0.0.01 2025-04-14 Feng Bohan initial version
//===========================================================================
interface chip_if(input bit clk);
logic rst_n;
logic cnt_en;
logic clear;
logic [7:0] cnt;
task init;
rst_n = 0;
cnt_en = 0;
clear = 0;
endtask
clocking ck_p @(posedge clk);
output rst_n;
output cnt_en;
output clear;
input cnt;
endclocking
modport DUT(clocking ck_p);
endinterface

33
5_clock_block/rtl/dut.sv Normal file
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//===========================================================================
// Organization : Individual developer
// Filename : dut.sv
// Author : Feng Bohan
// Create Time : 16:08:33 2025-04-14
// Last Modified: 16:13:43 2025-04-14
// Abstract :
//--------------------------------------------------------------------------
// Description:
//
//--------------------------------------------------------------------------
// Modification History:
//--------------------------------------------------------------------------
// Rev Date Who Description
// --- ---- --- -----------
// 0.0.01 2025-04-14 Feng Bohan initial version
//===========================================================================
module dut(
input clk,
input rst_n,
input cnt_en,
input clear,
output reg [7:0] cnt
);
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
cnt <= #1ns 0;
else if(clear == 1)
cnt <= #1ns 0;
else if(cnt_en== 1)
cnt <= #1ns cnt+1;
end
endmodule

48
5_clock_block/rtl/tb.sv Normal file
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//===========================================================================
// Organization : Individual developer
// Filename : tb.sv
// Author : Feng Bohan
// Create Time : 11:26:47 2025-03-18
// Last Modified: 11:27:17 2025-03-18
// Abstract :
//--------------------------------------------------------------------------
// Description:
//
//--------------------------------------------------------------------------
// Modification History:
//--------------------------------------------------------------------------
// Rev Date Who Description
// --- ---- --- -----------
// 0.0.01 2025-03-18 Feng Bohan initial version
//===========================================================================
module testbench;
localparam T = 10;
bit clk = 0;
always #(T/2) clk = ~clk;
chip_if co_if(clk);
initial begin
co_if.init;
@co_if.ck_p;
co_if.ck_p.rst_n <= 1;
@co_if.ck_p;
co_if.ck_p.cnt_en <= 1;
for(int i=0; i<10; i++) begin
@co_if.ck_p;
$display("cnt = %d", co_if.ck_p.cnt);
end
$finish(2);
end
dut u0_dut(
.clk (clk ),
.rst_n (co_if.rst_n ),
.cnt_en (co_if.cnt_en ),
.clear (co_if.clear ),
.cnt (co_if.cnt )
);
endmodule

78
5_clock_block/signal.rc Normal file
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Magic 271485
Revision Verdi_O-2018.09-SP2
; Window Layout <x> <y> <width> <height> <signalwidth> <valuewidth>
viewPort 0 27 1850 380 212 65
; File list:
; openDirFile [-d delimiter] [-s time_offset] [-rf auto_bus_rule_file] path_name file_name
openDirFile -d / "" "/home/fengbh/nasWork/sv_lab/5_clock_block/wave.fsdb"
; file time scale:
; fileTimeScale ### s|ms|us|ns|ps
; signal spacing:
signalSpacing 5
; windowTimeUnit is used for zoom, cursor & marker
; waveform viewport range
zoom 0.000000 471.232836
cursor 0.000000
marker 0.000000
; user define markers
; userMarker time_pos marker_name color linestyle
; visible top row signal index
top 0
; marker line index
markerPos 10
; event list
; addEvent event_name event_expression
; curEvent event_name
COMPLEX_EVENT_BEGIN
COMPLEX_EVENT_END
; toolbar current search type
; curSTATUS search_type
curSTATUS ByChange
addGroup "G1"
activeDirFile "" "/home/fengbh/nasWork/sv_lab/5_clock_block/wave.fsdb"
addSignal -h 15 /testbench/u0_dut/clk
addSignal -h 15 -holdScope rst_n
addSignal -h 15 -holdScope cnt_en
addSignal -h 15 -holdScope clear
addSignal -h 15 -holdScope cnt[7:0]
addGroup "G2"
addSignal -h 15 /testbench/co_if/ck_p/rst_n
addSignal -h 15 -holdScope cnt_en
addSignal -h 15 -holdScope clear
addSignal -h 15 -holdScope cnt[7:0]
addGroup "G3"
; getSignalForm Scope Hierarchy Status
; active file of getSignalForm
activeDirFile "" "/home/fengbh/nasWork/sv_lab/5_clock_block/wave.fsdb"
GETSIGNALFORM_SCOPE_HIERARCHY_BEGIN
getSignalForm close
"/testbench"
SCOPE_LIST_BEGIN
"/testbench"
"/testbench/u0_dut"
SCOPE_LIST_END
GETSIGNALFORM_SCOPE_HIERARCHY_END