From 325e97a7595e34d9c15245478a63cb7d127a8ea6 Mon Sep 17 00:00:00 2001 From: fengbh <1953356163@qq.com> Date: Thu, 5 Dec 2024 17:14:17 +0800 Subject: [PATCH] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E5=85=B6=E4=BB=96=E6=83=85?= =?UTF-8?q?=E5=86=B5=E7=9A=84=E5=AE=9E=E9=AA=8C?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- 2_vcs_comp/Makefile | 15 +++++++- 2_vcs_comp/ReadMe.md | 16 +++++++- 2_vcs_comp/rtl/counter_a.sv | 1 + 2_vcs_comp/rtl/counter_b.sv | 1 + 2_vcs_comp/rtl/counter_c.sv | 1 + .../rtl/{testbench.sv => testbench1.sv} | 10 +++-- 2_vcs_comp/rtl/testbench2.sv | 37 ++++++++++++++++++ 2_vcs_comp/rtl/testbench3.sv | 38 +++++++++++++++++++ 2_vcs_comp/rtl/testbench4.sv | 38 +++++++++++++++++++ 2_vcs_comp/tb_flist.f | 2 - 10 files changed, 151 insertions(+), 8 deletions(-) rename 2_vcs_comp/rtl/{testbench.sv => testbench1.sv} (93%) create mode 100644 2_vcs_comp/rtl/testbench2.sv create mode 100644 2_vcs_comp/rtl/testbench3.sv create mode 100644 2_vcs_comp/rtl/testbench4.sv delete mode 100644 2_vcs_comp/tb_flist.f diff --git a/2_vcs_comp/Makefile b/2_vcs_comp/Makefile index 3e0f300..affe89a 100644 --- a/2_vcs_comp/Makefile +++ b/2_vcs_comp/Makefile @@ -1,4 +1,17 @@ .PHONY: clean comp all +LAB = 1 +ifeq ($(LAB), 1) + TB_FILE = ./rtl/testbench1.sv +else ifeq ($(LAB), 2) + TB_FILE = ./rtl/testbench2.sv +else ifeq ($(LAB), 3) + TB_FILE = ./rtl/testbench3.sv +else ifeq ($(LAB), 4) + TB_FILE = ./rtl/testbench4.sv +else + TB_FILE = ./rtl/testbench1.sv +endif + GENLIB = 1 ifeq ($(GENLIB), 1) COMP_TB_ARG = +define+TEST1 @@ -28,7 +41,7 @@ endif comp_tb: - vlogan -full64 +v2k -sverilog \ -l compile_tb.log -timescale=1ns/1ps \ - -ntb_opts uvm-1.2 -f ./tb_flist.f ./partcfg.sv -work TB $(COMP_TB_ARG) + -ntb_opts uvm-1.2 $(TB_FILE) ./partcfg.sv -work TB $(COMP_TB_ARG) comp_elab: - vcs -full64 -sverilog -LDFLAGS -Wl,--no-as-need \ diff --git a/2_vcs_comp/ReadMe.md b/2_vcs_comp/ReadMe.md index 151ff45..cd3cf73 100644 --- a/2_vcs_comp/ReadMe.md +++ b/2_vcs_comp/ReadMe.md @@ -87,4 +87,18 @@ Note-[PC_RECOMPILE] Recompiling partition TB.testbench : "./rtl/testbench.sv", 20 ``` -检查log可以发现，穿层信号变化涉及到的模块`counter_b、counter_c`都无法reuse。 \ No newline at end of file +检查log可以发现，穿层信号变化涉及到的模块`counter_b、counter_c`都无法reuse。 + +## 结论 + +| 序号 | 条件 | 现象 | 结论 | 备注 | +| ---- | ----------------------------------------------------- | ------- | ---------------------------- | ---- | +| 1 | 第一次：引用a.name； 第二次引用a.name/b.name/c.name； | b/c重编 | 不同的模块，增加的引用会重编 | | +| 2 | 第一次：引用a.name；第二次引用a.age； | a重编 | 同一个模块，不同引用也会重编 | | +| 3 | 第一次：引用a.name/a.age；第二次引用a.name； | a重编 | 同一个模块，减少引用也会重编 | | +| 4 | 第一次：引用a.name；第二次引用a.name/a.age； | a重编 | 同一个模块，增加引用也会重编 | | + +⚠：只要模块的穿层引用发生变化，就会导致该模块重编。 + +✍官方文档VCSLCAFeatures.pdf第408页，也有类似表述：Any change in XMRs, trigger recompilation of the referee partition. + diff --git a/2_vcs_comp/rtl/counter_a.sv b/2_vcs_comp/rtl/counter_a.sv index 37ff27b..06379d9 100644 --- a/2_vcs_comp/rtl/counter_a.sv +++ b/2_vcs_comp/rtl/counter_a.sv @@ -17,4 +17,5 @@ //=========================================================================== module counter_a; string name = "counter_a"; + string age = "10"; endmodule diff --git a/2_vcs_comp/rtl/counter_b.sv b/2_vcs_comp/rtl/counter_b.sv index d65cff8..5e80693 100644 --- a/2_vcs_comp/rtl/counter_b.sv +++ b/2_vcs_comp/rtl/counter_b.sv @@ -17,4 +17,5 @@ //=========================================================================== module counter_b; string name = "counter_b"; + string age = "11"; endmodule diff --git a/2_vcs_comp/rtl/counter_c.sv b/2_vcs_comp/rtl/counter_c.sv index e21a1a8..31c1cd6 100644 --- a/2_vcs_comp/rtl/counter_c.sv +++ b/2_vcs_comp/rtl/counter_c.sv @@ -17,4 +17,5 @@ //=========================================================================== module counter_c; string name = "counter_c"; + string age = "12"; endmodule diff --git a/2_vcs_comp/rtl/testbench.sv b/2_vcs_comp/rtl/testbench1.sv similarity index 93% rename from 2_vcs_comp/rtl/testbench.sv rename to 2_vcs_comp/rtl/testbench1.sv index b9435ae..d760d09 100644 --- a/2_vcs_comp/rtl/testbench.sv +++ b/2_vcs_comp/rtl/testbench1.sv @@ -19,16 +19,18 @@ import uvm_pkg::*; module testbench; top dut_top(); -`ifdef TEST2 - string version = "test2"; -`else +`ifdef TEST1 string version = "test1"; +`else + string version = "test2"; `endif initial begin `uvm_info("testbench::", $sformatf("start %s", version), UVM_LOW) + `ifdef TEST1 + $display("sub_module name = %s", dut_top.a.name); + `else $display("sub_module name = %s", dut_top.a.name); - `ifdef TEST2 $display("sub_module name = %s", dut_top.b.name); $display("sub_module name = %s", dut_top.c.name); `endif diff --git a/2_vcs_comp/rtl/testbench2.sv b/2_vcs_comp/rtl/testbench2.sv new file mode 100644 index 0000000..f68659c --- /dev/null +++ b/2_vcs_comp/rtl/testbench2.sv @@ -0,0 +1,37 @@ +//=========================================================================== +// Organization : Individual Developer +// Filename : testbench.sv +// Author : Feng Bohan +// Create Time : 20:06:44 2024-12-02 +// Last Modified: 20:12:07 2024-12-02 +// Abstract : +//-------------------------------------------------------------------------- +// Description: +// +//-------------------------------------------------------------------------- +// Modification History: +//-------------------------------------------------------------------------- +// Rev Date Who Description +// --- ---- --- ----------- +// 0.0.01 2024-12-02 Feng Bohan initial version +//=========================================================================== +`include "uvm_macros.svh" +import uvm_pkg::*; +module testbench; + top dut_top(); +`ifdef TEST1 + string version = "test1"; +`else + string version = "test2"; +`endif + + initial begin + `uvm_info("testbench::", $sformatf("start %s", version), UVM_LOW) + `ifdef TEST1 + $display("sub_module name = %s", dut_top.a.name); + `else + $display("sub_module age = %s", dut_top.a.age); + `endif + `uvm_info("testbench::", $sformatf("finish %s", version), UVM_LOW) + end +endmodule diff --git a/2_vcs_comp/rtl/testbench3.sv b/2_vcs_comp/rtl/testbench3.sv new file mode 100644 index 0000000..d7932d6 --- /dev/null +++ b/2_vcs_comp/rtl/testbench3.sv @@ -0,0 +1,38 @@ +//=========================================================================== +// Organization : Individual Developer +// Filename : testbench.sv +// Author : Feng Bohan +// Create Time : 20:06:44 2024-12-02 +// Last Modified: 20:12:07 2024-12-02 +// Abstract : +//-------------------------------------------------------------------------- +// Description: +// +//-------------------------------------------------------------------------- +// Modification History: +//-------------------------------------------------------------------------- +// Rev Date Who Description +// --- ---- --- ----------- +// 0.0.01 2024-12-02 Feng Bohan initial version +//=========================================================================== +`include "uvm_macros.svh" +import uvm_pkg::*; +module testbench; + top dut_top(); +`ifdef TEST1 + string version = "test1"; +`else + string version = "test2"; +`endif + + initial begin + `uvm_info("testbench::", $sformatf("start %s", version), UVM_LOW) + `ifdef TEST1 + $display("sub_module name = %s", dut_top.a.name); + $display("sub_module age = %s", dut_top.a.age); + `else + $display("sub_module name = %s", dut_top.a.name); + `endif + `uvm_info("testbench::", $sformatf("finish %s", version), UVM_LOW) + end +endmodule diff --git a/2_vcs_comp/rtl/testbench4.sv b/2_vcs_comp/rtl/testbench4.sv new file mode 100644 index 0000000..dcc3248 --- /dev/null +++ b/2_vcs_comp/rtl/testbench4.sv @@ -0,0 +1,38 @@ +//=========================================================================== +// Organization : Individual Developer +// Filename : testbench.sv +// Author : Feng Bohan +// Create Time : 20:06:44 2024-12-02 +// Last Modified: 20:12:07 2024-12-02 +// Abstract : +//-------------------------------------------------------------------------- +// Description: +// +//-------------------------------------------------------------------------- +// Modification History: +//-------------------------------------------------------------------------- +// Rev Date Who Description +// --- ---- --- ----------- +// 0.0.01 2024-12-02 Feng Bohan initial version +//=========================================================================== +`include "uvm_macros.svh" +import uvm_pkg::*; +module testbench; + top dut_top(); +`ifdef TEST1 + string version = "test1"; +`else + string version = "test2"; +`endif + + initial begin + `uvm_info("testbench::", $sformatf("start %s", version), UVM_LOW) + `ifdef TEST1 + $display("sub_module name = %s", dut_top.a.name); + `else + $display("sub_module name = %s", dut_top.a.name); + $display("sub_module age = %s", dut_top.a.age); + `endif + `uvm_info("testbench::", $sformatf("finish %s", version), UVM_LOW) + end +endmodule diff --git a/2_vcs_comp/tb_flist.f b/2_vcs_comp/tb_flist.f deleted file mode 100644 index ab193b0..0000000 --- a/2_vcs_comp/tb_flist.f +++ /dev/null @@ -1,2 +0,0 @@ -./rtl/testbench.sv -