This commit is contained in:
fengbh 2025-03-19 16:30:51 +08:00
parent 532a3227f1
commit 68bcc3fb47
3 changed files with 113 additions and 0 deletions

2
.gitignore vendored
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@ -4,9 +4,11 @@ simv.daidir
*.key
*.log
*.swp
.vscode
2_vcs_comp/tb_lib/
2_vcs_comp/dut_lib/
2_vcs_comp/partitionlib/
2_vcs_comp/vc_hdrs.h
2_vcs_comp/partitionlib_test2/
3_timing_check/

30
4_class/Makefile Normal file
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@ -0,0 +1,30 @@
LSB_RELEASE = $(shell lsb_release -is)
LSB_VERSION = $(shell lsb_release -rs)
ifeq (${LSB_RELEASE}, Ubuntu)
ifeq ($(shell echo "${LSB_VERSION}>18.04" | bc), 1)
CC = gcc-4.8
CPP = g++-4.8
else
CC = gcc
CPP = g++
endif
else
CC = gcc
CPP = g++
endif
VCC = vcs -full64 +v2k -sverilog -LDFLAGS -Wl,--no-as-needed -cc $(CC) -cpp $(CPP)\
-P ${VERDI_HOME}/share/PLI/VCS/LINUX64/novas.tab ${VERDI_HOME}/share/PLI/VCS/LINUX64/pli.a
.PHONY: clean comp all
clean:
- rm -rf csrc simv.daidir ucli.key *.log simv
comp:
$(VCC) -debug_access+all -kdb -top tb -l compile.log -timescale=1ns/1ps ./rtl/tb.sv
sim:
- ./simv -l sim.log
all: comp sim

81
4_class/rtl/tb.sv Normal file
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//===========================================================================
// Organization : Individual developer
// Filename : tb.sv
// Author : Feng Bohan
// Create Time : 11:26:47 2025-03-18
// Last Modified: 11:27:17 2025-03-18
// Abstract :
//--------------------------------------------------------------------------
// Description:
//
//--------------------------------------------------------------------------
// Modification History:
//--------------------------------------------------------------------------
// Rev Date Who Description
// --- ---- --- -----------
// 0.0.01 2025-03-18 Feng Bohan initial version
//===========================================================================
module tb();
class BasePacket;
int A; // 1;
int B; // 2;
int C; // 3;
function new(int A=1, int B=2, int C=3);
this.A=A;
this.B=B;
this.C=C;
endfunction
virtual function void printA;
$display("[%m] A is %0d", A);
endfunction
virtual function void printB;
$display("[%m] B is %0d", B);
endfunction : printB
function void printC;
$display("[%m] C is %0d", C);
endfunction : printC
endclass : BasePacket
class My_Packet extends BasePacket;
int A; // 4
int B; // 5
int C; // 6
function new(int A=4, int B=5, int C=6);
this.A=A;
this.B=B;
this.C=C;
endfunction
/* -----\/----- EXCLUDED -----\/-----
virtual function void printA;
$display("A is %0d", A);
endfunction
-----/\----- EXCLUDED -----/\----- */
virtual function void printB;
$display("[%m] B is %0d", B);
endfunction : printB
function void printC;
$display("[%m] C is %0d", C);
endfunction : printC
endclass : My_Packet
initial begin
BasePacket P1;
My_Packet P2 = new;
P1 = P2; // P1 has a handle to a My_packet object
$display("//******************** P1.print ********************");
P1.printA; // A is 1
P1.printB; // B is 4
P1.printC; // B is 4
$display("//**************************************************");
$display("//******************** P2.print ********************");
P2.printA; // A is 1
P2.printB; // B is 4
P2.printC; // B is 4
$display("//**************************************************");
end
endmodule // tb