From e6efeec30801bb124e4fd933f22616841895c067 Mon Sep 17 00:00:00 2001
From: fengbh <1953356163@qq.com>
Date: Mon, 2 Dec 2024 14:34:53 +0800
Subject: [PATCH] add 1_hierarchy

---
 .gitignore               |  5 ++++
 1_hierarchy/Makefile     | 14 +++++++++++
 1_hierarchy/ReadMe.md    | 34 +++++++++++++++++++++++++++
 1_hierarchy/testbench.sv | 50 ++++++++++++++++++++++++++++++++++++++++
 ReadMe.md                |  7 +++---
 5 files changed, 107 insertions(+), 3 deletions(-)
 create mode 100644 .gitignore
 create mode 100644 1_hierarchy/Makefile
 create mode 100644 1_hierarchy/ReadMe.md
 create mode 100644 1_hierarchy/testbench.sv

diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..1deb92a
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,5 @@
+csrc
+simv
+simv.daidir
+*.key
+*.log
diff --git a/1_hierarchy/Makefile b/1_hierarchy/Makefile
new file mode 100644
index 0000000..7403f31
--- /dev/null
+++ b/1_hierarchy/Makefile
@@ -0,0 +1,14 @@
+.PHONY: clean comp all
+
+clean:
+	- rm -rf csrc simv.daidir ucli.key *.log simv
+
+comp:
+	- vcs -full64 +v2k -sverilog -LDFLAGS -Wl,--no-as-need \
+		-top testbench -l compile.log -timescale=1ns/1ps \
+		testbench.sv
+
+sim:
+	./simv -l sim.log
+
+all: clean comp sim
diff --git a/1_hierarchy/ReadMe.md b/1_hierarchy/ReadMe.md
new file mode 100644
index 0000000..bdc4c91
--- /dev/null
+++ b/1_hierarchy/ReadMe.md
@@ -0,0 +1,34 @@
+# 层次路径解析
+
+sv当前模块对层次路径的解析：
+
+- 绝对路径：支持从顶层模块名开始，一路`.`下来。如`testbench.a1.data`
+- 相对路径：
+  - 支持从**父级模块名**开始，一路`.`下来。如`A.data`
+  - 支持使用当前模块内的**实例化名**，一路`.`下来。如`a1.data`
+
+这个项目主要是为了验证：可以使用==从父级模块名开始的相对路径解析==。当检查多次例化的模块，或模块层级不确定时可以简化代码。
+
+## 快速开始
+
+```bash
+make all
+```
+
+## 运行结果
+
+```
+Chronologic VCS simulator copyright 1991-2018
+Contains Synopsys proprietary information.
+Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64;  Dec  2 14:29 2024
+testbench.a1.data = 1
+a1.data = 1
+A.data = 1
+A.data = 2
+A.data = 3
+           V C S   S i m u l a t i o n   R e p o r t 
+Time: 0 ps
+CPU Time:      0.210 seconds;       Data structure size:   0.0Mb
+Mon Dec  2 14:29:12 2024
+```
+
diff --git a/1_hierarchy/testbench.sv b/1_hierarchy/testbench.sv
new file mode 100644
index 0000000..193df85
--- /dev/null
+++ b/1_hierarchy/testbench.sv
@@ -0,0 +1,50 @@
+//=========================================================================== 
+// Organization : Individual Developer 
+// Filename     : testbench.sv
+// Author       : Feng Bohan
+// Create Time  : 16:44:54 2024-11-29
+// Last Modified: 17:04:34 2024-11-29
+// Abstract     :  
+//--------------------------------------------------------------------------
+// Description:
+// 
+//--------------------------------------------------------------------------
+// Modification History:
+//--------------------------------------------------------------------------
+// Rev      Date        Who         Description
+// ---      ----        ---         -----------
+// 0.0.01   2024-11-29  Feng Bohan  initial version
+//===========================================================================
+module B;
+    initial begin
+        $display("A.data = %0d", A.data);
+    end
+endmodule
+
+module A #(
+    parameter DATA = 0
+)();
+    reg [31:0] data = DATA;
+    B b();
+endmodule
+
+module testbench;
+    A #(
+        .DATA(1)
+    )a1();
+
+    A #(
+        .DATA(2)
+    )a2();
+
+    A #(
+        .DATA(3)
+    )a3();
+
+    initial begin
+        $display("testbench.a1.data = %0d", testbench.a1.data);
+        $display("a1.data = %0d", a1.data);
+    end
+endmodule
+
+
diff --git a/ReadMe.md b/ReadMe.md
index ec56380..fbaf8ee 100644
--- a/ReadMe.md
+++ b/ReadMe.md
@@ -4,6 +4,7 @@ sv_lib是一系列systemverilog lab的合集，帮助学习sv的特性。
 
 ## 项目列表
 
-| 项目 | 描述 | 状态 | 备注 |
-| ---- | ---- | ---- | ---- |
-|      |      |      |      |
\ No newline at end of file
+| 项目                         | 描述                 | 状态   | 备注 |
+| ---------------------------- | -------------------- | ------ | ---- |
+| [1_hierarchy](./1_hierarchy) | 对层次路径的解析测试 | 开发中 |      |
+