//=========================================================================== 
// Organization : Individual developer 
// Filename     : chip_if.sv
// Author       : Feng Bohan
// Create Time  : 16:14:12 2025-04-14
// Last Modified: 16:21:05 2025-04-14
// Abstract     :  
//--------------------------------------------------------------------------
// Description:
// 
//--------------------------------------------------------------------------
// Modification History:
//--------------------------------------------------------------------------
// Rev      Date        Who         Description
// ---      ----        ---         -----------
// 0.0.01   2025-04-14  Feng Bohan  initial version
//===========================================================================
interface chip_if(input bit clk);
    logic rst_n;
    logic cnt_en;
    logic clear;
    logic [7:0] cnt;

    clocking ck_p @(posedge clk);
        default input #1ns output #1ns;
        output rst_n;
        output cnt_en;
        output clear;
        input cnt;
    endclocking

    task init;
        ck_p.rst_n <= 0;
        ck_p.cnt_en <= 0;
        ck_p.clear <= 0;
        @ck_p;
    endtask

    modport DUT(clocking ck_p);
        
endinterface