//=========================================================================== 
// Organization : Individual developer 
// Filename     : dut.sv
// Author       : Feng Bohan
// Create Time  : 16:08:33 2025-04-14
// Last Modified: 16:13:43 2025-04-14
// Abstract     :  
//--------------------------------------------------------------------------
// Description:
// 
//--------------------------------------------------------------------------
// Modification History:
//--------------------------------------------------------------------------
// Rev      Date        Who         Description
// ---      ----        ---         -----------
// 0.0.01   2025-04-14  Feng Bohan  initial version
//===========================================================================
module dut(
    input clk,
    input rst_n,
    input cnt_en,
    input clear,
    output reg [7:0] cnt
);
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n)
            cnt <= #1ns 0;
        else if(clear == 1)
            cnt <=  #1ns 0;
        else if(cnt_en== 1)
            cnt <=  #1ns cnt+1;
    end
endmodule