/**
 * File              : tb.sv
 * License           : MIT
 * Author            : Feng Bohan <1953356163@qq.com>
 * Date              : 2025-04-30 16:04:53
 * Last Modified Date: 2025-05-22 15:33:46
 * Last Modified By  : Feng Bohan <1953356163@qq.com>
 * -----
 * Copyright © 2025 Feng Bohan. All Rights Reserved.
 */
//typedef class sim_common;
module testbench;
    localparam T = 10;  
    bit clk = 0;
    always #(T/2) clk = ~clk;

    chip_if co_if(clk);

    initial begin
      co_if.init;

      @co_if.ck_p;
      co_if.ck_p.rst_n <= 1;

      @co_if.ck_p;
      co_if.ck_p.cnt_en <= 1;
      for(int i=0; i<10; i++) begin
        @co_if.ck_p;
        $display("cnt = %d", co_if.ck_p.cnt);
      end
      @co_if.ck_p;
      co_if.ck_p.clear <= 1;
      @co_if.ck_p;
      co_if.ck_p.clear <= 0;
      for(int i=0; i<10; i++) begin
        @co_if.ck_p;
        $display("cnt = %d", co_if.ck_p.cnt);
      end
      $finish(2);
    end

    dut u0_dut(
        .clk    (clk          ),
        .rst_n  (co_if.rst_n  ),
        .cnt_en (co_if.cnt_en ),
        .clear  (co_if.clear  ),
        .cnt    (co_if.cnt    )
    );

endmodule