/**
 * File              : dut.sv
 * License           : MIT
 * Author            : Feng Bohan <1953356163@qq.com>
 * Date              : 2025-05-22 15:37:52
 * Last Modified Date: 2025-05-22 16:41:45
 * Last Modified By  : Feng Bohan <1953356163@qq.com>
 * -----
 * Copyright © 2025 Feng Bohan. All Rights Reserved.
 */
module counter(
    input clk,
    input rst_n,
    input cnt_en,
    input cnt_clr,
    output reg [7:0] cnt
);
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            cnt <= 0;
        end else begin
            if(cnt_clr == 1) begin
                cnt <= 0;
            end else if(cnt_en)begin
                cnt <= cnt +1;
            end
        end
    end
endmodule