module dut(
    input clk,
    input rst_n,
    input cnt_en,
    input clear,
    output reg [7:0] cnt
);
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n)
            cnt <= #1ns 0;
        else if(clear == 1)
            cnt <=  #1ns 0;
        else if(cnt_en== 1)
            cnt <=  #1ns cnt+1;
    end
endmodule