40 lines
1.4 KiB
Systemverilog
40 lines
1.4 KiB
Systemverilog
//===========================================================================
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// Organization : Individual Developer
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// Filename : testbench.sv
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// Author : Feng Bohan
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// Create Time : 20:06:44 2024-12-02
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// Last Modified: 20:12:07 2024-12-02
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// Abstract :
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//--------------------------------------------------------------------------
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// Description:
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//
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//--------------------------------------------------------------------------
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// Modification History:
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//--------------------------------------------------------------------------
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// Rev Date Who Description
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// --- ---- --- -----------
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// 0.0.01 2024-12-02 Feng Bohan initial version
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//===========================================================================
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`include "uvm_macros.svh"
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import uvm_pkg::*;
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module testbench;
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top dut_top();
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`ifdef TEST1
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string version = "test1";
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`else
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string version = "test2";
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`endif
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initial begin
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`uvm_info("testbench::", $sformatf("start %s", version), UVM_LOW)
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`ifdef TEST1
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$display("sub_module name = %s", dut_top.a.name);
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`else
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$display("sub_module name = %s", dut_top.a.name);
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$display("sub_module name = %s", dut_top.b.name);
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$display("sub_module name = %s", dut_top.c.name);
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`endif
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`uvm_info("testbench::", $sformatf("finish %s", version), UVM_LOW)
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end
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endmodule
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