59 lines
1.6 KiB
Systemverilog
59 lines
1.6 KiB
Systemverilog
//===========================================================================
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// Organization : Individual developer
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// Filename : tb.sv
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// Author : Feng Bohan
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// Create Time : 11:26:47 2025-03-18
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// Last Modified: 11:27:17 2025-03-18
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// Abstract :
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//--------------------------------------------------------------------------
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// Description:
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//
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//--------------------------------------------------------------------------
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// Modification History:
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//--------------------------------------------------------------------------
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// Rev Date Who Description
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// --- ---- --- -----------
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// 0.0.01 2025-03-18 Feng Bohan initial version
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//===========================================================================
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module tb;
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int a ;
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task automatic stable_a( ref int a_ip );
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bit change_;
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fork
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begin
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fork
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begin:T1
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@(a_ip);
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change_++;
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end
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begin:T2
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#5ns;
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end
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join_any
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disable fork;
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if( !change_ )
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$display("T:%0t Input arg. unchanged",$time); // Should observe this for +define+M1
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else
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$display("T:%0t Input arg. changed",$time); // Should observe this for +define+M2 / +define+M3
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end
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join
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endtask
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initial begin
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stable_a(a);
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end
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initial begin
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`ifdef M1
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#6;
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`elsif M2
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#4 a = 10;
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`elsif M3
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#5 a = 20;
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`endif
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end
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endmodule |