56 lines
1.5 KiB
Systemverilog
56 lines
1.5 KiB
Systemverilog
//===========================================================================
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// Organization : Individual developer
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// Filename : tb.sv
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// Author : Feng Bohan
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// Create Time : 11:26:47 2025-03-18
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// Last Modified: 11:27:17 2025-03-18
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// Abstract :
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//--------------------------------------------------------------------------
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// Description:
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//
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//--------------------------------------------------------------------------
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// Modification History:
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//--------------------------------------------------------------------------
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// Rev Date Who Description
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// --- ---- --- -----------
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// 0.0.01 2025-03-18 Feng Bohan initial version
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//===========================================================================
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module testbench;
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localparam T = 10;
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bit clk = 0;
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always #(T/2) clk = ~clk;
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chip_if co_if(clk);
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initial begin
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co_if.init;
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@co_if.ck_p;
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co_if.ck_p.rst_n <= 1;
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@co_if.ck_p;
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co_if.ck_p.cnt_en <= 1;
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for(int i=0; i<10; i++) begin
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@co_if.ck_p;
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$display("cnt = %d", co_if.ck_p.cnt);
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end
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@co_if.ck_p;
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co_if.ck_p.clear <= 1;
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@co_if.ck_p;
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co_if.ck_p.clear <= 0;
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for(int i=0; i<10; i++) begin
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@co_if.ck_p;
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$display("cnt = %d", co_if.ck_p.cnt);
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end
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$finish(2);
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end
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dut u0_dut(
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.clk (clk ),
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.rst_n (co_if.rst_n ),
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.cnt_en (co_if.cnt_en ),
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.clear (co_if.clear ),
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.cnt (co_if.cnt )
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);
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endmodule |