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fengbh c735390e5f init
2024-12-02 11:43:07 +08:00
ReadMe.md
init
2024-12-02 11:43:07 +08:00

ReadMe.md

sv_lib

sv_lib是一系列systemverilog lab的合集，帮助学习sv的特性。

项目列表

项目 描述 状态 备注
Description
No description provided
Readme 158 KiB
Languages
SystemVerilog 83.1%
Makefile 16%
Forth 0.6%
Tcl 0.3%