43 lines
1.2 KiB
Systemverilog
43 lines
1.2 KiB
Systemverilog
//===========================================================================
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// Organization : Individual developer
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// Filename : chip_if.sv
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// Author : Feng Bohan
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// Create Time : 16:14:12 2025-04-14
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// Last Modified : 2025/04/30 16:26
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// Abstract :
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//--------------------------------------------------------------------------
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// Description:
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//
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//--------------------------------------------------------------------------
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// Modification History:
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//--------------------------------------------------------------------------
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// Rev Date Who Description
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// --- ---- --- -----------
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// 0.0.01 2025-04-14 Feng Bohan initial version
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//===========================================================================
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interface chip_if(input bit clk);
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logic rst_n;
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logic cnt_en;
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logic clear;
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logic [7:0] cnt;
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clocking ck_p @(posedge clk);
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default input #1ns output #1ns;
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output rst_n;
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output cnt_en;
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output clear;
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input cnt;
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endclocking
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task init;
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ck_p.rst_n <= 0;
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ck_p.cnt_en <= 0;
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ck_p.clear <= 0;
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@ck_p;
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endtask
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modport DUT(ck_p);
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endinterface
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