51 lines
1.1 KiB
Systemverilog
51 lines
1.1 KiB
Systemverilog
/**
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* File : tb.sv
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* License : MIT
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* Author : Feng Bohan <1953356163@qq.com>
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* Date : 2025-04-30 16:04:53
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* Last Modified Date: 2025-05-22 15:33:46
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* Last Modified By : Feng Bohan <1953356163@qq.com>
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* -----
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* Copyright © 2025 Feng Bohan. All Rights Reserved.
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*/
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//typedef class sim_common;
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module testbench;
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localparam T = 10;
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bit clk = 0;
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always #(T/2) clk = ~clk;
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chip_if co_if(clk);
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initial begin
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co_if.init;
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@co_if.ck_p;
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co_if.ck_p.rst_n <= 1;
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@co_if.ck_p;
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co_if.ck_p.cnt_en <= 1;
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for(int i=0; i<10; i++) begin
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@co_if.ck_p;
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$display("cnt = %d", co_if.ck_p.cnt);
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end
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@co_if.ck_p;
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co_if.ck_p.clear <= 1;
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@co_if.ck_p;
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co_if.ck_p.clear <= 0;
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for(int i=0; i<10; i++) begin
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@co_if.ck_p;
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$display("cnt = %d", co_if.ck_p.cnt);
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end
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$finish(2);
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end
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dut u0_dut(
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.clk (clk ),
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.rst_n (co_if.rst_n ),
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.cnt_en (co_if.cnt_en ),
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.clear (co_if.clear ),
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.cnt (co_if.cnt )
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);
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endmodule
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