38 lines
1.1 KiB
Systemverilog
38 lines
1.1 KiB
Systemverilog
//===========================================================================
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// Organization : Individual Developer
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// Filename : testbench.sv
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// Author : Feng Bohan
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// Create Time : 12:54:11 2024-11-21
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// Last Modified: 13:49:31 2024-11-21
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// Abstract :
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//--------------------------------------------------------------------------
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// Description:
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//
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//--------------------------------------------------------------------------
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// Modification History:
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//--------------------------------------------------------------------------
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// Rev Date Who Description
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// --- ---- --- -----------
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// 0.0.01 2024-11-21 Feng Bohan initial version
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//===========================================================================
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`timescale 1ns / 1ns
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module testbench;
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reg clk=0, rst_n=1;
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always #5 clk = ~clk;
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reg [7:0] cnt;
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always @(posedge clk or negedge rst_n)
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if(!rst_n)
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cnt <= 0;
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else
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cnt <= cnt +1;
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initial begin
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rst_n = 0;
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#10 rst_n =1;
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$display("Hello world!");
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#1000 $finish;
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end
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endmodule
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