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fengbh 2024-12-06 13:53:45 +08:00
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ReadMe.md
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@ -7,5 +7,5 @@ sv_lib是一系列systemverilog lab的合集，帮助学习sv的特性。
| 项目 | 描述 | 状态 | 备注 |
| ---------------------------- | ---------------------------------- | ---- | ---- |
| [1_hierarchy](./1_hierarchy) | 对层次路径的解析测试 | 100% | |
| [2_vcs_comp](./2_vcs_comp) | 使用三步编译和分块编译加快编译速度 | 80% | |
| [2_vcs_comp](./2_vcs_comp) | 使用三步编译和分块编译加快编译速度 | 100% | |