更新新项目

0_test/Makefile

@@ -0,0 +1,30 @@
+
+LSB_RELEASE = $(shell lsb_release -is)
+LSB_VERSION = $(shell lsb_release -rs)
+ifeq (${LSB_RELEASE}, Ubuntu)
+	ifeq ($(shell echo "${LSB_VERSION}>18.04" | bc), 1)
+    	CC = gcc-4.8
+		CPP = g++-4.8
+	else
+    	CC = gcc
+		CPP = g++
+	endif
+else
+    CC = gcc
+	CPP = g++
+endif
+VCC = vcs -full64 +v2k -sverilog -LDFLAGS -Wl,--no-as-needed -cc $(CC) -cpp $(CPP)\
+		-P ${VERDI_HOME}/share/PLI/VCS/LINUX64/novas.tab ${VERDI_HOME}/share/PLI/VCS/LINUX64/pli.a
+
+.PHONY: clean comp all
+
+clean:
+	- rm -rf csrc simv.daidir ucli.key *.log simv
+
+comp:
+	$(VCC) -debug_access+all -kdb -top tb -l compile.log -timescale=1ns/1ps ./rtl/tb.sv
+
+sim:
+	- ./simv -l sim.log
+
+all: comp sim

0_test/rtl/tb.sv

@@ -0,0 +1,59 @@
+//=========================================================================== 
+// Organization : Individual developer 
+// Filename     : tb.sv
+// Author       : Feng Bohan
+// Create Time  : 11:26:47 2025-03-18
+// Last Modified: 11:27:17 2025-03-18
+// Abstract     :  
+//--------------------------------------------------------------------------
+// Description:
+// 
+//--------------------------------------------------------------------------
+// Modification History:
+//--------------------------------------------------------------------------
+// Rev      Date        Who         Description
+// ---      ----        ---         -----------
+// 0.0.01   2025-03-18  Feng Bohan  initial version
+//===========================================================================
+module tb;  
+  int a ;
+  
+  task automatic stable_a( ref int a_ip );
+    bit change_;  
+    fork
+     begin 
+      
+      fork        
+       begin:T1
+         @(a_ip);
+         change_++;     
+       end         
+       begin:T2
+         #5ns;         
+       end                  
+      join_any    
+      disable fork;
+        
+      if( !change_ ) 
+        $display("T:%0t Input arg. unchanged",$time); // Should observe this for +define+M1
+      else
+        $display("T:%0t Input arg. changed",$time); // Should observe this for +define+M2 / +define+M3
+        
+     end  
+    join     
+  endtask  
+    
+  initial begin    
+    stable_a(a);
+  end  
+       
+  initial begin    
+    `ifdef M1     
+      #6;     
+    `elsif M2    
+      #4 a = 10;    
+    `elsif M3    
+      #5 a = 20;    
+    `endif            
+  end  
+endmodule

ReadMe.md

@@ -8,4 +8,7 @@ sv_lib是一系列systemverilog lab的合集，帮助学习sv的特性。
 | ---------------------------- | ---------------------------------- | ---- | ---- |
 | [1_hierarchy](./1_hierarchy) | 对层次路径的解析测试                | 100% |      |
 | [2_vcs_comp](./2_vcs_comp)   | 使用三步编译和分块编译加快编译速度   | 100% |      |
+| [3_timing_check](./3_timing_check)         | 时序检查函数相关研究                | 50% |      |
+| [4_class](./4_class)         | 基类和扩展类关系研究                | 100% |      |
+| [5_clock_block](./5_clock_block)         | 研究时钟块的延时                | 0% |      |