add 2_vcs_comp

.gitignore

@@ -3,3 +3,10 @@ simv
 simv.daidir
 *.key
 *.log
+*.swp
+
+2_vcs_comp/tb_lib/
+2_vcs_comp/dut_lib/
+2_vcs_comp/partitionlib/
+2_vcs_comp/vc_hdrs.h
+2_vcs_comp/partitionlib_test2/

2_vcs_comp/Makefile

@@ -0,0 +1,44 @@
+.PHONY: clean comp all
+GENLIB = 1
+ifeq ($(GENLIB), 1)
+	COMP_TB_ARG = +define+TEST1
+	PART_ARG = -partcomp_dir=./partitionlib
+else
+	COMP_TB_ARG = +define+TEST2
+	PART_ARG = -partcomp_dir=./partitionlib_test2 -partcomp_sharedlib=./partitionlib 
+endif
+
+clean:
+	- rm -rf csrc simv.daidir ucli.key *.log simv
+
+comp_dut:
+ifeq ($(GENLIB),1)
+	- vlogan -full64 +v2k -sverilog \
+		-l compile_dut.log -timescale=1ns/1ps \
+		-f ./dut_flist.f -work WORK
+endif
+
+comp_uvm:
+ifeq ($(GENLIB),1)
+	- vlogan -full64 +v2k -sverilog \
+		-l compile_uvm.log -timescale=1ns/1ps \
+		-ntb_opts uvm-1.2 -work WORK
+endif
+
+comp_tb:
+	- vlogan -full64 +v2k -sverilog \
+		-l compile_tb.log -timescale=1ns/1ps \
+		-ntb_opts uvm-1.2 -f ./tb_flist.f ./partcfg.sv -work TB $(COMP_TB_ARG)
+
+comp_elab:
+	- vcs -full64 -sverilog -LDFLAGS -Wl,--no-as-need \
+		-l compile_elab.log -timescale=1ns/1ps \
+		-ntb_opts uvm-1.2 -lca\
+		-partcomp -top TB.partcfg -fastpartcomp=j4 $(PART_ARG) \
+		-pcmakeprof
+	
+comp: comp_dut comp_uvm comp_tb comp_elab
+
+sim:
+	./simv -l sim.log +UVM_NO_RELNOTES
+all: comp sim

2_vcs_comp/ReadMe.md

@@ -0,0 +1,90 @@
+# VCS编译加速：三步编译和分块编译
+
+验证问题：有不同穿层信号时，模块的partition库能否reuse?
+
+结论：**当穿层信号变化时，受影响的模块不能reuse**。
+
+## 快速开始
+
+### 第一次编译
+
+```bash
+make all GENLIB=1
+```
+
+### 第二次编译
+
+```bash
+make all GENLIB=0
+```
+
+## 运行结果
+
+```
+Top Level Modules:
+       testbench
+TimeScale is 1 ns / 1 ps
+
+Note-[PC_SHARED] Reusing shared partition
+  Reusing partition '_vcs_pc_package_' from shared library './partitionlib'.
+
+
+
+Note-[PC_SHARED] Reusing shared partition
+  Reusing partition 'uvm_pkg' from shared library './partitionlib'.
+
+
+
+Note-[PC_SHARED] Reusing shared partition
+  Reusing partition 'counter_a' from shared library './partitionlib'.
+
+
+
+Warning-[PC_NOT_SHARED] Cannot reuse shared partition
+  Cannot reuse partition 'counter_b' from shared library './partitionlib'
+
+  There are additional signals that are now targets of hierarchical
+  references.
+
+
+
+Note-[PC_GEN_PARTITION] Generating partition
+  Generating new partition 'counter_b' at
+  './partitionlib_test2/counter_b_ipFRWc'.
+
+
+Warning-[PC_NOT_SHARED] Cannot reuse shared partition
+  Cannot reuse partition 'counter_c' from shared library './partitionlib'
+
+  There are additional signals that are now targets of hierarchical
+  references.
+
+
+
+Note-[PC_GEN_PARTITION] Generating partition
+  Generating new partition 'counter_c' at
+  './partitionlib_test2/counter_c_chn5zb'.
+
+
+Note-[PC_SHARED] Reusing shared partition
+  Reusing partition 'top' from shared library './partitionlib'.
+
+
+
+Warning-[PC_NOT_SHARED] Cannot reuse shared partition
+  Cannot reuse partition 'TB.testbench' from shared library './partitionlib'
+
+  Modified Design Units :
+        TB.testbench : "./rtl/testbench.sv", 20
+  Type of targets of hierarchical references in this partition have changed.
+
+
+
+Note-[PC_RECOMPILE] Recompiling partition
+  Recompiling partition 'TB.testbench' because of following changes.
+
+  Modified Design Units :
+        TB.testbench : "./rtl/testbench.sv", 20
+```
+
+检查log可以发现，穿层信号变化涉及到的模块`counter_b、counter_c`都无法reuse。

2_vcs_comp/dut_flist.f

@@ -0,0 +1,4 @@
+./rtl/counter_a.sv
+./rtl/counter_b.sv
+./rtl/counter_c.sv
+./rtl/top.sv

2_vcs_comp/partcfg.sv

@@ -0,0 +1,26 @@
+//=========================================================================== 
+// Organization : Individual Developer 
+// Filename     : partcfg.sv
+// Author       : Feng Bohan
+// Create Time  : 20:20:36 2024-12-02
+// Last Modified: 20:34:34 2024-12-02
+// Abstract     :  
+//--------------------------------------------------------------------------
+// Description:
+// 
+//--------------------------------------------------------------------------
+// Modification History:
+//--------------------------------------------------------------------------
+// Rev      Date        Who         Description
+// ---      ----        ---         -----------
+// 0.0.01   2024-12-02  Feng Bohan  initial version
+//===========================================================================
+config partcfg;
+    design testbench;
+    default liblist WORK TB;
+    partition cell counter_a;
+    partition cell counter_b;
+    partition cell counter_c;
+    partition instance testbench.dut_top;
+    partition package uvm_pkg;
+endconfig

2_vcs_comp/rtl/counter_a.sv

@@ -0,0 +1,20 @@
+//=========================================================================== 
+// Organization : Individual Developer 
+// Filename     : counter_a.sv
+// Author       : Feng Bohan
+// Create Time  : 20:04:22 2024-12-02
+// Last Modified: 20:05:23 2024-12-02
+// Abstract     :  
+//--------------------------------------------------------------------------
+// Description:
+// 
+//--------------------------------------------------------------------------
+// Modification History:
+//--------------------------------------------------------------------------
+// Rev      Date        Who         Description
+// ---      ----        ---         -----------
+// 0.0.01   2024-12-02  Feng Bohan  initial version
+//===========================================================================
+module counter_a;
+    string name = "counter_a";
+endmodule

2_vcs_comp/rtl/counter_b.sv

@@ -0,0 +1,20 @@
+//=========================================================================== 
+// Organization : Individual Developer 
+// Filename     : counter_b.sv
+// Author       : Feng Bohan
+// Create Time  : 20:05:28 2024-12-02
+// Last Modified: 20:05:39 2024-12-02
+// Abstract     :  
+//--------------------------------------------------------------------------
+// Description:
+// 
+//--------------------------------------------------------------------------
+// Modification History:
+//--------------------------------------------------------------------------
+// Rev      Date        Who         Description
+// ---      ----        ---         -----------
+// 0.0.01   2024-12-02  Feng Bohan  initial version
+//===========================================================================
+module counter_b;
+    string name = "counter_b";
+endmodule

2_vcs_comp/rtl/counter_c.sv

@@ -0,0 +1,20 @@
+//=========================================================================== 
+// Organization : Individual Developer 
+// Filename     : counter_c.sv
+// Author       : Feng Bohan
+// Create Time  : 20:05:42 2024-12-02
+// Last Modified: 20:05:52 2024-12-02
+// Abstract     :  
+//--------------------------------------------------------------------------
+// Description:
+// 
+//--------------------------------------------------------------------------
+// Modification History:
+//--------------------------------------------------------------------------
+// Rev      Date        Who         Description
+// ---      ----        ---         -----------
+// 0.0.01   2024-12-02  Feng Bohan  initial version
+//===========================================================================
+module counter_c;
+    string name = "counter_c";
+endmodule

2_vcs_comp/rtl/testbench.sv

@@ -0,0 +1,37 @@
+//=========================================================================== 
+// Organization : Individual Developer 
+// Filename     : testbench.sv
+// Author       : Feng Bohan
+// Create Time  : 20:06:44 2024-12-02
+// Last Modified: 20:12:07 2024-12-02
+// Abstract     :  
+//--------------------------------------------------------------------------
+// Description:
+// 
+//--------------------------------------------------------------------------
+// Modification History:
+//--------------------------------------------------------------------------
+// Rev      Date        Who         Description
+// ---      ----        ---         -----------
+// 0.0.01   2024-12-02  Feng Bohan  initial version
+//===========================================================================
+`include "uvm_macros.svh"
+import uvm_pkg::*;
+module testbench;
+    top dut_top();
+`ifdef TEST2
+    string version = "test2";
+`else
+    string version = "test1";
+`endif
+
+    initial begin
+        `uvm_info("testbench::", $sformatf("start %s", version), UVM_LOW)
+        $display("sub_module name = %s", dut_top.a.name);
+    `ifdef TEST2
+        $display("sub_module name = %s", dut_top.b.name);
+        $display("sub_module name = %s", dut_top.c.name);
+    `endif
+        `uvm_info("testbench::", $sformatf("finish %s", version), UVM_LOW)
+    end
+endmodule

2_vcs_comp/rtl/top.sv

@@ -0,0 +1,22 @@
+//=========================================================================== 
+// Organization : Individual Developer 
+// Filename     : top.sv
+// Author       : Feng Bohan
+// Create Time  : 20:03:18 2024-12-02
+// Last Modified: 20:04:04 2024-12-02
+// Abstract     :  
+//--------------------------------------------------------------------------
+// Description:
+// 
+//--------------------------------------------------------------------------
+// Modification History:
+//--------------------------------------------------------------------------
+// Rev      Date        Who         Description
+// ---      ----        ---         -----------
+// 0.0.01   2024-12-02  Feng Bohan  initial version
+//===========================================================================
+module top;
+    counter_a a();
+    counter_b b();
+    counter_c c();
+endmodule

2_vcs_comp/synopsys_sim.setup

@@ -0,0 +1,3 @@
+WORK > DEFAULT
+DEFAULT : ./dut_lib
+TB : ./tb_lib

2_vcs_comp/tb_flist.f

@@ -0,0 +1,2 @@
+./rtl/testbench.sv
+

ReadMe.md

@@ -4,7 +4,8 @@ sv_lib是一系列systemverilog lab的合集，帮助学习sv的特性。
 
 ## 项目列表
 
-| 项目                         | 描述                 | 状态   | 备注 |
-| ---------------------------- | -------------------- | ------ | ---- |
-| [1_hierarchy](./1_hierarchy) | 对层次路径的解析测试 | 开发中 |      |
+| 项目                         | 描述                               | 状态 | 备注 |
+| ---------------------------- | ---------------------------------- | ---- | ---- |
+| [1_hierarchy](./1_hierarchy) | 对层次路径的解析测试               | 100% |      |
+| [2_vcs_comp](./2_vcs_comp)   | 使用三步编译和分块编译加快编译速度 | 80%  |      |