21 lines
836 B
Systemverilog
21 lines
836 B
Systemverilog
//===========================================================================
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// Organization : Individual Developer
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// Filename : counter_a.sv
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// Author : Feng Bohan
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// Create Time : 20:04:22 2024-12-02
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// Last Modified: 20:05:23 2024-12-02
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// Abstract :
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//--------------------------------------------------------------------------
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// Description:
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//
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//--------------------------------------------------------------------------
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// Modification History:
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//--------------------------------------------------------------------------
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// Rev Date Who Description
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// --- ---- --- -----------
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// 0.0.01 2024-12-02 Feng Bohan initial version
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//===========================================================================
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module counter_a;
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string name = "counter_a";
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endmodule
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