sv_lab/1_hierarchy/ReadMe.md
2024-12-02 14:34:53 +08:00

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# 层次路径解析
sv当前模块对层次路径的解析
- 绝对路径:支持从顶层模块名开始,一路`.`下来。如`testbench.a1.data`
- 相对路径:
- 支持从**父级模块名**开始,一路`.`下来。如`A.data`
- 支持使用当前模块内的**实例化名**,一路`.`下来。如`a1.data`
这个项目主要是为了验证:可以使用==从父级模块名开始的相对路径解析==。当检查多次例化的模块,或模块层级不确定时可以简化代码。
## 快速开始
```bash
make all
```
## 运行结果
```
Chronologic VCS simulator copyright 1991-2018
Contains Synopsys proprietary information.
Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64; Dec 2 14:29 2024
testbench.a1.data = 1
a1.data = 1
A.data = 1
A.data = 2
A.data = 3
V C S S i m u l a t i o n R e p o r t
Time: 0 ps
CPU Time: 0.210 seconds; Data structure size: 0.0Mb
Mon Dec 2 14:29:12 2024
```