34 lines
1.1 KiB
Systemverilog
34 lines
1.1 KiB
Systemverilog
//===========================================================================
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// Organization : Individual developer
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// Filename : dut.sv
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// Author : Feng Bohan
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// Create Time : 16:08:33 2025-04-14
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// Last Modified: 16:13:43 2025-04-14
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// Abstract :
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//--------------------------------------------------------------------------
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// Description:
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//
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//--------------------------------------------------------------------------
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// Modification History:
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//--------------------------------------------------------------------------
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// Rev Date Who Description
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// --- ---- --- -----------
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// 0.0.01 2025-04-14 Feng Bohan initial version
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//===========================================================================
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module dut(
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input clk,
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input rst_n,
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input cnt_en,
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input clear,
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output reg [7:0] cnt
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);
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always@(posedge clk or negedge rst_n) begin
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if(!rst_n)
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cnt <= #1ns 0;
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else if(clear == 1)
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cnt <= #1ns 0;
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else if(cnt_en== 1)
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cnt <= #1ns cnt+1;
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end
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endmodule
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