30 lines
729 B
Systemverilog
30 lines
729 B
Systemverilog
/**
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* File : dut.sv
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* License : MIT
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* Author : Feng Bohan <1953356163@qq.com>
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* Date : 2025-05-22 15:37:52
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* Last Modified Date: 2025-05-22 16:41:45
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* Last Modified By : Feng Bohan <1953356163@qq.com>
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* -----
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* Copyright © 2025 Feng Bohan. All Rights Reserved.
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*/
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module counter(
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input clk,
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input rst_n,
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input cnt_en,
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input cnt_clr,
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output reg [7:0] cnt
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);
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always @(posedge clk or negedge rst_n) begin
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if(!rst_n) begin
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cnt <= 0;
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end else begin
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if(cnt_clr == 1) begin
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cnt <= 0;
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end else if(cnt_en)begin
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cnt <= cnt +1;
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end
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end
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end
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endmodule
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