51 lines
1.2 KiB
Systemverilog
51 lines
1.2 KiB
Systemverilog
//===========================================================================
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// Organization : Individual Developer
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// Filename : testbench.sv
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// Author : Feng Bohan
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// Create Time : 16:44:54 2024-11-29
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// Last Modified: 17:04:34 2024-11-29
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// Abstract :
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//--------------------------------------------------------------------------
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// Description:
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//
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//--------------------------------------------------------------------------
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// Modification History:
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//--------------------------------------------------------------------------
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// Rev Date Who Description
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// --- ---- --- -----------
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// 0.0.01 2024-11-29 Feng Bohan initial version
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//===========================================================================
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module B;
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initial begin
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$display("A.data = %0d", A.data);
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end
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endmodule
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module A #(
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parameter DATA = 0
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)();
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reg [31:0] data = DATA;
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B b();
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endmodule
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module testbench;
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A #(
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.DATA(1)
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)a1();
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A #(
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.DATA(2)
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)a2();
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A #(
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.DATA(3)
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)a3();
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initial begin
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$display("testbench.a1.data = %0d", testbench.a1.data);
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$display("a1.data = %0d", a1.data);
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end
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endmodule
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