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fengbh 2025-05-22 15:37:02 +08:00
parent 2187679d7c
commit d20c70dc3d
4 changed files with 23 additions and 42 deletions
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4
.gitignore vendored
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@ -16,3 +16,7 @@ simv.daidir
2_vcs_comp/partitionlib_test2/ 2_vcs_comp/partitionlib_test2/
3_timing_check/ 3_timing_check/
5_clock_block/verdiLog/ 5_clock_block/verdiLog/
5_clock_block/rtl/AN.DB
5_clock_block/rtl/tags
5_clock_block/rtl/xsim.dir
5_clock_block/rtl/xvlog.pb

4
5_clock_block/rtl/chip_if.sv
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@ -3,7 +3,7 @@
// Filename : chip_if.sv // Filename : chip_if.sv
// Author : Feng Bohan // Author : Feng Bohan
// Create Time : 16:14:12 2025-04-14 // Create Time : 16:14:12 2025-04-14
// Last Modified: 16:21:05 2025-04-14 // Last Modified : 2025/04/30 16:26
// Abstract : // Abstract :
//-------------------------------------------------------------------------- //--------------------------------------------------------------------------
// Description: // Description:
@ -36,7 +36,7 @@ interface chip_if(input bit clk);
@ck_p; @ck_p;
endtask endtask
modport DUT(clocking ck_p); modport DUT(ck_p);
endinterface endinterface

17
5_clock_block/rtl/dut.sv
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@ -1,20 +1,3 @@
//===========================================================================
// Organization : Individual developer
// Filename : dut.sv
// Author : Feng Bohan
// Create Time : 16:08:33 2025-04-14
// Last Modified: 16:13:43 2025-04-14
// Abstract :
//--------------------------------------------------------------------------
// Description:
//
//--------------------------------------------------------------------------
// Modification History:
//--------------------------------------------------------------------------
// Rev Date Who Description
// --- ---- --- -----------
// 0.0.01 2025-04-14 Feng Bohan initial version
//===========================================================================
module dut( module dut(
input clk, input clk,
input rst_n, input rst_n,

40
5_clock_block/rtl/tb.sv
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@ -1,20 +1,14 @@
//=========================================================================== /**
// Organization : Individual developer * File : tb.sv
// Filename : tb.sv * License : MIT
// Author : Feng Bohan * Author : Feng Bohan <1953356163@qq.com>
// Create Time : 11:26:47 2025-03-18 * Date : 2025-04-30 16:04:53
// Last Modified: 11:27:17 2025-03-18 * Last Modified Date: 2025-05-22 15:33:46
// Abstract : * Last Modified By : Feng Bohan <1953356163@qq.com>
//-------------------------------------------------------------------------- * -----
// Description: * Copyright © 2025 Feng Bohan. All Rights Reserved.
// */
//-------------------------------------------------------------------------- //typedef class sim_common;
// Modification History:
//--------------------------------------------------------------------------
// Rev Date Who Description
// --- ---- --- -----------
// 0.0.01 2025-03-18 Feng Bohan initial version
//===========================================================================
module testbench; module testbench;
localparam T = 10; localparam T = 10;
bit clk = 0; bit clk = 0;
@ -46,11 +40,11 @@ module testbench;
end end
dut u0_dut( dut u0_dut(
.clk (clk ), .clk (clk ),
.rst_n (co_if.rst_n ), .rst_n (co_if.rst_n ),
.cnt_en (co_if.cnt_en ), .cnt_en (co_if.cnt_en ),
.clear (co_if.clear ), .clear (co_if.clear ),
.cnt (co_if.cnt ) .cnt (co_if.cnt )
); );
endmodule endmodule