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ReadMe.md

sv_lib

sv_lib是一系列systemverilog lab的合集，帮助学习sv的特性。

项目列表

项目 描述 状态 备注
1_hierarchy 对层次路径的解析测试 100%
2_vcs_comp 使用三步编译和分块编译加快编译速度 100%
Description
No description provided
Readme 158 KiB
Languages
SystemVerilog 83.1%
Makefile 16%
Forth 0.6%
Tcl 0.3%