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8
.gitignore vendored
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@ -4,15 +4,9 @@ simv.daidir
*.key *.key
*.log *.log
*.swp *.swp
.vscode
*/vc_hdrs.h
*/novas.rc
*/novas.conf
*.fsdb
2_vcs_comp/tb_lib/ 2_vcs_comp/tb_lib/
2_vcs_comp/dut_lib/ 2_vcs_comp/dut_lib/
2_vcs_comp/partitionlib/ 2_vcs_comp/partitionlib/
2_vcs_comp/vc_hdrs.h
2_vcs_comp/partitionlib_test2/ 2_vcs_comp/partitionlib_test2/
3_timing_check/
5_clock_block/verdiLog/

30
0_test/Makefile
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@ -1,30 +0,0 @@
LSB_RELEASE = $(shell lsb_release -is)
LSB_VERSION = $(shell lsb_release -rs)
ifeq (${LSB_RELEASE}, Ubuntu)
ifeq ($(shell echo "${LSB_VERSION}>18.04" | bc), 1)
CC = gcc-4.8
CPP = g++-4.8
else
CC = gcc
CPP = g++
endif
else
CC = gcc
CPP = g++
endif
VCC = vcs -full64 +v2k -sverilog -LDFLAGS -Wl,--no-as-needed -cc $(CC) -cpp $(CPP)\
-P ${VERDI_HOME}/share/PLI/VCS/LINUX64/novas.tab ${VERDI_HOME}/share/PLI/VCS/LINUX64/pli.a
.PHONY: clean comp all
clean:
- rm -rf csrc simv.daidir ucli.key *.log simv
comp:
$(VCC) -debug_access+all -kdb -top tb -l compile.log -timescale=1ns/1ps ./rtl/tb.sv
sim:
- ./simv -l sim.log
all: comp sim

59
0_test/rtl/tb.sv
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@ -1,59 +0,0 @@
//===========================================================================
// Organization : Individual developer
// Filename : tb.sv
// Author : Feng Bohan
// Create Time : 11:26:47 2025-03-18
// Last Modified: 11:27:17 2025-03-18
// Abstract :
//--------------------------------------------------------------------------
// Description:
//
//--------------------------------------------------------------------------
// Modification History:
//--------------------------------------------------------------------------
// Rev Date Who Description
// --- ---- --- -----------
// 0.0.01 2025-03-18 Feng Bohan initial version
//===========================================================================
module tb;
int a ;
task automatic stable_a( ref int a_ip );
bit change_;
fork
begin
fork
begin:T1
@(a_ip);
change_++;
end
begin:T2
#5ns;
end
join_any
disable fork;
if( !change_ )
$display("T:%0t Input arg. unchanged",$time); // Should observe this for +define+M1
else
$display("T:%0t Input arg. changed",$time); // Should observe this for +define+M2 / +define+M3
end
join
endtask
initial begin
stable_a(a);
end
initial begin
`ifdef M1
#6;
`elsif M2
#4 a = 10;
`elsif M3
#5 a = 20;
`endif
end
endmodule

126
2_vcs_comp/ReadMe.md
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@ -20,132 +20,6 @@ make all LAB=1 GENLIB=1
make all LAB=1 GENLIB=0 make all LAB=1 GENLIB=0
``` ```
## 实验框架
### 实验一
```mermaid
flowchart LR
tb["testbench1"]
dut["top"]
tb --> dut
dut --> ca
dut ----> cb
dut ------> cc
tb -.第一次.-> namea
tb -.第二次.-> namea
tb -.第二次.-> nameb
tb -.第二次.-> namec
subgraph ca[counter_a]
direction LR
namea["name = counter_a"]
agea["age = 10"]
end
subgraph cb[counter_b]
direction LR
nameb["name = counter_b"]
ageb["age = 11"]
end
subgraph cc[counter_c]
direction LR
namec["name = counter_c"]
agec["age = 12"]
end
```
### 实验二
```mermaid
flowchart LR
tb["testbench2"]
dut["top"]
tb --> dut
dut --> ca
dut ----> cb
dut ------> cc
tb -.第一次.-> namea
tb -.第二次.-> agea
subgraph ca[counter_a]
direction LR
namea["name = counter_a"]
agea["age = 10"]
end
subgraph cb[counter_b]
direction LR
nameb["name = counter_b"]
ageb["age = 11"]
end
subgraph cc[counter_c]
direction LR
namec["name = counter_c"]
agec["age = 12"]
end
```
### 实验三
```mermaid
flowchart LR
tb["testbench3"]
dut["top"]
tb --> dut
dut --> ca
dut ----> cb
dut ------> cc
tb -.第一次.-> namea
tb -.第一次.-> agea
tb -.第二次.-> namea
subgraph ca[counter_a]
direction LR
namea["name = counter_a"]
agea["age = 10"]
end
subgraph cb[counter_b]
direction LR
nameb["name = counter_b"]
ageb["age = 11"]
end
subgraph cc[counter_c]
direction LR
namec["name = counter_c"]
agec["age = 12"]
end
```
### 实验四
```mermaid
flowchart LR
tb["testbench4"]
dut["top"]
tb --> dut
dut --> ca
dut ----> cb
dut ------> cc
tb -.第一次.-> namea
tb -.第二次.-> namea
tb -.第二次.-> agea
subgraph ca[counter_a]
direction LR
namea["name = counter_a"]
agea["age = 10"]
end
subgraph cb[counter_b]
direction LR
nameb["name = counter_b"]
ageb["age = 11"]
end
subgraph cc[counter_c]
direction LR
namec["name = counter_c"]
agec["age = 12"]
end
```
## 结论 ## 结论
| 序号 | 条件 | 现象 | 结论 | 备注 | | 序号 | 条件 | 现象 | 结论 | 备注 |

30
4_class/Makefile
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@ -1,30 +0,0 @@
LSB_RELEASE = $(shell lsb_release -is)
LSB_VERSION = $(shell lsb_release -rs)
ifeq (${LSB_RELEASE}, Ubuntu)
ifeq ($(shell echo "${LSB_VERSION}>18.04" | bc), 1)
CC = gcc-4.8
CPP = g++-4.8
else
CC = gcc
CPP = g++
endif
else
CC = gcc
CPP = g++
endif
VCC = vcs -full64 +v2k -sverilog -LDFLAGS -Wl,--no-as-needed -cc $(CC) -cpp $(CPP)\
-P ${VERDI_HOME}/share/PLI/VCS/LINUX64/novas.tab ${VERDI_HOME}/share/PLI/VCS/LINUX64/pli.a
.PHONY: clean comp all
clean:
- rm -rf csrc simv.daidir ucli.key *.log simv
comp:
$(VCC) -debug_access+all -kdb -top tb -l compile.log -timescale=1ns/1ps ./rtl/tb.sv
sim:
- ./simv -l sim.log
all: comp sim

38
4_class/ReadMe.md
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@ -1,38 +0,0 @@
# 基类和扩展类关系研究
验证问题：基类和扩展类之间变量、函数、重载、虚拟方法等之间的关系是怎样的，要如何理解。
结论：类由变量和函数组成，扩展类可以理解在基类的基础上增加了一个类。但是有几点需要注意：
* 基类和扩展类的**变量空间彼此独立**，即使同名。
* 基类和扩展类的**函数空间彼此独立**，即使同名。
* 基类函数只能访问基类变量，扩展类函数只能访问扩展类变量。
* **基类访问扩展类变量的唯一方法就是使用重载后的函数（虚拟方法）。**
* **virtual声明的函数，会覆盖父类中的同名函数。**。
## 快速开始
```bash
make all
```
### 输入结果
```text
Chronologic VCS simulator copyright 1991-2018
Contains Synopsys proprietary information.
Compiler version O-2018.09-SP2_Full64; Runtime version O-2018.09-SP2_Full64; Mar 19 16:29 2025
//******************** P1.print ********************
[tb.\BasePacket::printA ] A is 1
[tb.\My_Packet::printB ] B is 5
[tb.\BasePacket::printC ] C is 3
//**************************************************
//******************** P2.print ********************
[tb.\BasePacket::printA ] A is 1
[tb.\My_Packet::printB ] B is 5
[tb.\My_Packet::printC ] C is 6
//**************************************************
V C S S i m u l a t i o n R e p o r t
Time: 0 ps
CPU Time: 0.130 seconds; Data structure size: 0.0Mb
Wed Mar 19 16:29:22 2025
```

81
4_class/rtl/tb.sv
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@ -1,81 +0,0 @@
//===========================================================================
// Organization : Individual developer
// Filename : tb.sv
// Author : Feng Bohan
// Create Time : 11:26:47 2025-03-18
// Last Modified: 11:27:17 2025-03-18
// Abstract :
//--------------------------------------------------------------------------
// Description:
//
//--------------------------------------------------------------------------
// Modification History:
//--------------------------------------------------------------------------
// Rev Date Who Description
// --- ---- --- -----------
// 0.0.01 2025-03-18 Feng Bohan initial version
//===========================================================================
module tb();
class BasePacket;
int A; // 1;
int B; // 2;
int C; // 3;
function new(int A=1, int B=2, int C=3);
this.A=A;
this.B=B;
this.C=C;
endfunction
virtual function void printA;
$display("[%m] A is %0d", A);
endfunction
virtual function void printB;
$display("[%m] B is %0d", B);
endfunction : printB
function void printC;
$display("[%m] C is %0d", C);
endfunction : printC
endclass : BasePacket
class My_Packet extends BasePacket;
int A; // 4
int B; // 5
int C; // 6
function new(int A=4, int B=5, int C=6);
this.A=A;
this.B=B;
this.C=C;
endfunction
/* -----\/----- EXCLUDED -----\/-----
virtual function void printA;
$display("A is %0d", A);
endfunction
-----/\----- EXCLUDED -----/\----- */
virtual function void printB;
$display("[%m] B is %0d", B);
endfunction : printB
function void printC;
$display("[%m] C is %0d", C);
endfunction : printC
endclass : My_Packet
initial begin
BasePacket P1;
My_Packet P2 = new;
P1 = P2; // P1 has a handle to a My_packet object
$display("//******************** P1.print ********************");
P1.printA;
P1.printB;
P1.printC;
$display("//**************************************************");
$display("//******************** P2.print ********************");
P2.printA;
P2.printB;
P2.printC;
$display("//**************************************************");
end
endmodule // tb

30
5_clock_block/Makefile
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@ -1,30 +0,0 @@
LSB_RELEASE = $(shell lsb_release -is)
LSB_VERSION = $(shell lsb_release -rs)
ifeq (${LSB_RELEASE}, Ubuntu)
ifeq ($(shell echo "${LSB_VERSION}>18.04" | bc), 1)
CC = gcc-4.8
CPP = g++-4.8
else
CC = gcc
CPP = g++
endif
else
CC = gcc
CPP = g++
endif
VCC = vcs -full64 +v2k -sverilog -LDFLAGS -Wl,--no-as-needed -cc $(CC) -cpp $(CPP)\
-P ${VERDI_HOME}/share/PLI/VCS/LINUX64/novas.tab ${VERDI_HOME}/share/PLI/VCS/LINUX64/pli.a
.PHONY: clean comp all
clean:
- rm -rf csrc simv.daidir ucli.key *.log simv
comp:
$(VCC) -debug_access+all -debug_region=cell+lib -kdb -top testbench -l compile.log -timescale=1ns/1ps -f filelist.f
sim:
- ./simv -l sim.log +fsdb+all=on +fsdb+delta +fsdbfile+./wave.fsdb -ucli -i fsdb.tcl
all: comp sim

3
5_clock_block/filelist.f
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@ -1,3 +0,0 @@
./rtl/tb.sv
./rtl/dut.sv
./rtl/chip_if.sv

2
5_clock_block/fsdb.tcl
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@ -1,2 +0,0 @@
fsdbDumpvars 0 testbench
run

42
5_clock_block/rtl/chip_if.sv
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@ -1,42 +0,0 @@
//===========================================================================
// Organization : Individual developer
// Filename : chip_if.sv
// Author : Feng Bohan
// Create Time : 16:14:12 2025-04-14
// Last Modified: 16:21:05 2025-04-14
// Abstract :
//--------------------------------------------------------------------------
// Description:
//
//--------------------------------------------------------------------------
// Modification History:
//--------------------------------------------------------------------------
// Rev Date Who Description
// --- ---- --- -----------
// 0.0.01 2025-04-14 Feng Bohan initial version
//===========================================================================
interface chip_if(input bit clk);
logic rst_n;
logic cnt_en;
logic clear;
logic [7:0] cnt;
clocking ck_p @(posedge clk);
default input #1ns output #1ns;
output rst_n;
output cnt_en;
output clear;
input cnt;
endclocking
task init;
ck_p.rst_n <= 0;
ck_p.cnt_en <= 0;
ck_p.clear <= 0;
@ck_p;
endtask
modport DUT(clocking ck_p);
endinterface

33
5_clock_block/rtl/dut.sv
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@ -1,33 +0,0 @@
//===========================================================================
// Organization : Individual developer
// Filename : dut.sv
// Author : Feng Bohan
// Create Time : 16:08:33 2025-04-14
// Last Modified: 16:13:43 2025-04-14
// Abstract :
//--------------------------------------------------------------------------
// Description:
//
//--------------------------------------------------------------------------
// Modification History:
//--------------------------------------------------------------------------
// Rev Date Who Description
// --- ---- --- -----------
// 0.0.01 2025-04-14 Feng Bohan initial version
//===========================================================================
module dut(
input clk,
input rst_n,
input cnt_en,
input clear,
output reg [7:0] cnt
);
always@(posedge clk or negedge rst_n) begin
if(!rst_n)
cnt <= #1ns 0;
else if(clear == 1)
cnt <= #1ns 0;
else if(cnt_en== 1)
cnt <= #1ns cnt+1;
end
endmodule

56
5_clock_block/rtl/tb.sv
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@ -1,56 +0,0 @@
//===========================================================================
// Organization : Individual developer
// Filename : tb.sv
// Author : Feng Bohan
// Create Time : 11:26:47 2025-03-18
// Last Modified: 11:27:17 2025-03-18
// Abstract :
//--------------------------------------------------------------------------
// Description:
//
//--------------------------------------------------------------------------
// Modification History:
//--------------------------------------------------------------------------
// Rev Date Who Description
// --- ---- --- -----------
// 0.0.01 2025-03-18 Feng Bohan initial version
//===========================================================================
module testbench;
localparam T = 10;
bit clk = 0;
always #(T/2) clk = ~clk;
chip_if co_if(clk);
initial begin
co_if.init;
@co_if.ck_p;
co_if.ck_p.rst_n <= 1;
@co_if.ck_p;
co_if.ck_p.cnt_en <= 1;
for(int i=0; i<10; i++) begin
@co_if.ck_p;
$display("cnt = %d", co_if.ck_p.cnt);
end
@co_if.ck_p;
co_if.ck_p.clear <= 1;
@co_if.ck_p;
co_if.ck_p.clear <= 0;
for(int i=0; i<10; i++) begin
@co_if.ck_p;
$display("cnt = %d", co_if.ck_p.cnt);
end
$finish(2);
end
dut u0_dut(
.clk (clk ),
.rst_n (co_if.rst_n ),
.cnt_en (co_if.cnt_en ),
.clear (co_if.clear ),
.cnt (co_if.cnt )
);
endmodule

78
5_clock_block/signal.rc
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@ -1,78 +0,0 @@
Magic 271485
Revision Verdi_O-2018.09-SP2
; Window Layout <x> <y> <width> <height> <signalwidth> <valuewidth>
viewPort 0 27 1850 384 212 65
; File list:
; openDirFile [-d delimiter] [-s time_offset] [-rf auto_bus_rule_file] path_name file_name
openDirFile -d / "" "/home/fengbh/nasWork/sv_lab/5_clock_block/wave.fsdb"
; file time scale:
; fileTimeScale ### s|ms|us|ns|ps
; signal spacing:
signalSpacing 5
; windowTimeUnit is used for zoom, cursor & marker
; waveform viewport range
zoom 0.000000 247450.000000
cursor 25000.000000
marker 0.000000
; user define markers
; userMarker time_pos marker_name color linestyle
; visible top row signal index
top 0
; marker line index
markerPos 10
; event list
; addEvent event_name event_expression
; curEvent event_name
COMPLEX_EVENT_BEGIN
COMPLEX_EVENT_END
; toolbar current search type
; curSTATUS search_type
curSTATUS ByChange
addGroup "G1"
activeDirFile "" "/home/fengbh/nasWork/sv_lab/5_clock_block/wave.fsdb"
addSignal -h 15 /testbench/u0_dut/clk
addSignal -h 15 -holdScope rst_n
addSignal -h 15 -holdScope cnt_en
addSignal -h 15 -holdScope clear
addSignal -h 15 -UNSIGNED -UDEC -holdScope cnt[7:0]
addGroup "G2"
addSignal -h 15 /testbench/co_if/ck_p/rst_n
addSignal -h 15 -holdScope cnt_en
addSignal -h 15 -holdScope clear
addSignal -h 15 -UNSIGNED -UDEC -holdScope cnt[7:0]
addGroup "G3"
; getSignalForm Scope Hierarchy Status
; active file of getSignalForm
activeDirFile "" "/home/fengbh/nasWork/sv_lab/5_clock_block/wave.fsdb"
GETSIGNALFORM_SCOPE_HIERARCHY_BEGIN
getSignalForm close
"/testbench"
SCOPE_LIST_BEGIN
"/testbench"
"/testbench/u0_dut"
SCOPE_LIST_END
GETSIGNALFORM_SCOPE_HIERARCHY_END

7
ReadMe.md
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@ -6,9 +6,6 @@ sv_lib是一系列systemverilog lab的合集，帮助学习sv的特性。
| 项目 | 描述 | 状态 | 备注 | | 项目 | 描述 | 状态 | 备注 |
| ---------------------------- | ---------------------------------- | ---- | ---- | | ---------------------------- | ---------------------------------- | ---- | ---- |
| [1_hierarchy](./1_hierarchy) | 对层次路径的解析测试 | 100% | | | [1_hierarchy](./1_hierarchy) | 对层次路径的解析测试 | 100% | |
| [2_vcs_comp](./2_vcs_comp) | 使用三步编译和分块编译加快编译速度 | 100% | | | [2_vcs_comp](./2_vcs_comp) | 使用三步编译和分块编译加快编译速度 | 80% | |
| [3_timing_check](./3_timing_check) | 时序检查函数相关研究 | 50% | |
| [4_class](./4_class) | 基类和扩展类关系研究 | 100% | |
| [5_clock_block](./5_clock_block) | 研究时钟块的延时 | 0% | |